15 Jan
2009
15 Jan
'09
1:36 p.m.
On Thu, Jan 15, 2009 at 1:25 PM, John Floren <slawmaster at gmail.com> wrote:
On Wed, Jan 14, 2009 at 6:46 PM, Guy Sotomayor <ggs
at shiresoft.com> wrote:
> Actually, he's gotten pretty far on it. I just talked to him today about
> it. I'd have to go back and look at my e-mail archives but late Nov/Dec he
> had it passing all of the DEC CPU diagnostics on a verilog simulator. Today
> he told me how many FFs & LUTs it took (not as much as he thought) to
> implement a KA10 style CPU (so he's doing synthesis).
Nice. Thanks for the update, Guy.
Promising! I've wanted to see a -10 in FPGA for a
while now, never had
the ambition (or the hardware) to try writing one in VHDL or anything.
Good luck to Dave, I guess.
As I mentioned the other night, I'm peripherally interested in an
FPGA-implemented -10, but I have a definite budget - I'm willing to
roll a lot of my own hardware (loose parts, soldering, etc), but I
really can't justify more than a few hundred $$$ in total. I
certainly can't assist with the VHDL-end of things.
Once things get past the experimental stage and it's booting TOPS-20,
I'm likely to be more interested. My requirements are pretty loose -
if it runs one of the extant compiled versions of MDL Zork, I'm in.
-ethan