6 Jan
2002
6 Jan
'02
1:34 p.m.
The PLL that seems to work the best for MFM is one that's in quadrature with
the data in a sync field such that the VCO goes high 90 degrees before the
sync waveform does. When there's a transition during the positive phase of
the VCO, the data, presumably, but only if verified by some unique data
pattern (Address Mark) or other signal, is a one. There are other approaches
based on 2x clocks that accomplish the same decoding using two-bit codes, but
if a timer is reset to the nominal bit window in quadrature with the negative
transitions on the data stream, it doesn't matter which approach you use.
For that PDP-8 controller, it would be useful to know the precise timing
relationship between the sector pulse and the next valid bit, including the
jitter. Once that's know, the recovery of data should be straightforward.
The common thing used in data recovery circuits for MFM was an 8T20, which,
IIRC, was a bidirectional one-shot. Such a function is ideally suited for
recovering ones from the modulated stream. The same could be produced,
methinks, with the state of the MFM latched at the leading edge of that data
window to which I referred above, and the MFM then XOR'd with that during the
window. If there's a transition, then there's a one. Otherwise, well, it's
not a one. I'm puzzled at how one is supposed to discriminate between clock
and data without Address Marks that have "missing" clocks. Unless the
relationship between the sector flag and the record ID are quite precise and
stabile, I'd say reliability is in trouble.
As for simply entering the schematic into the CPLD software and running a fit,
I'd feel quite comfortable that a '70's design would work find so long as all
events are synchronized to a single clock and that all "one-shot" events are
digitally synthesized in sync with the global clock. Because all the
macrocells in a CPLD are just that, as opposed to lookup tables as they are in
FPGA's, the "schematic of yesteryear" can be made to fit quite
realistically,
particularly in timing. Moreover, since most of the macrocells are directly
associated with pins, they're quite observable at the device boundaries so you
can hook your 'scope or logic analyzer to them if you like. You can do the
same with an FPGA, but I believe the CPLD is inherently better suited for
simple import of already working schematic designs.
The software's free, so give it a try!
Dick
----- Original Message -----
From: "Ben Franchuk" <bfranchuk(a)jetnet.ab.ca>
To: <classiccmp(a)classiccmp.org>
Sent: Sunday, January 06, 2002 6:51 PM
Subject: Re: MFM IC's (Was RE: Any AMIGA users?)
Richard Erlacher wrote:
> Another option would be to try to fit the schematic-based design of the
> original controller into a CPLD. (NOT and FPGA!!!) I've found that
> schematics of "old" logic seem to yield useable circuits in CPLD's,
while
> FPGA's totally seem to want to ruin the timing. That would lead to a
circuit
> about the size of half a dollar, that's
easily modifiable, since the parts
are
in-circuit-reprogrammable.
I never really trusted FPGA timing. I expect that unless you have
oneshots or glitch sets and clears timing should be simple.
None the less you do need to know what your logic does!
I think a digital data separator is just a counter that clocks
a shift register, with timing reset by the data stream.
Busy cooking supper so I can't look up more info.
--
Ben Frantic - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html