"Imaging" a MFM drive?

Al Kossow wrote: Interesting. I'm doing basically the same thing. Just found out this morning that almost the entire disc reader logic module was unstable -- it passes testbench perfectly, but won't work in hardware. Seems to be a fairly simple issue, but I've gone back to getting the drive stepping / status readback working over USB and adding some "fast register access" functions to the microcontroller first. The RAM read/write and USB stuff works really nicely, though. So basically I have a 512Kbyte, USB-interfaced SRAM :) I did some back-of-the-envelope calculations a while ago -- An ST412 will allow a maximum of 5e6 flux transitions per second. 1/5e6 = 200 nanoseconds between two flux transitions (worst case) The Catweasel's clock oscillator is switchable between: - 7.080MHz - 14.161MHz - 28.332MHz (Mk3 and Mk4 only) Which gives a timing resolution of: - 7.080MHz -- 141.2429 nanoseconds - 14.161MHz -- 70.6165 nanoseconds - 28.332MHz -- 35.2958 nanoseconds None of these are factors of 200ns, even if we ignore the fractional part; thus any measured timing values will be subject to a fair amount of jitter (around the 1-2 clock cycles mark). This would probably be masked by the inherent inaccuracy of the drive's spindle motor, though. Taking the coding into account, standard MFM has a minimum of 1T (200ns) and a maximum of 2T (400ns) between two transitions -- there's also the possibility of a 1.5T (300ns) delay between transitions. Using the fastest clock rate (28.332MHz)... - At 1T, you'll get a count of 5.6664. The CW can't count in fractions, so you'll see a count of 5. - At 1.5T, you'll see a count of 8.4996. The fraction is dropped, leaving a count of 8. - At 2T, you'll see a count of 11.3328. Again, the fraction is dropped, thus you see a count of 11. Decoding this would be possible, but wouldn't leave much room for error. If you had a "late" transition followed by an "early" transition, the difference in counts between two transitions could be as little as one clock. Even if the gap was wider, it'd still be hard to say with 100% certainty "this is a 01 sequence" or "this is a 001 sequence". I'm using a 40MHz primary clock reference in my disc analyser for a few reasons: - It makes the math easy. 40MHz = 25ns per count. - 25ns is an integer factor of the bit-cell sizes and transition periods used on floppy discs. It also ties in nicely with the transition rates used on MFM HDDs, assuming you don't want to write back to the drive. The 25ns resolution of a 40MHz oscillator gives a 1T count of 8, a 1.5T count of 12, and a 2T count of 16. Even with a worst-case jitter of 2 cycles, you still have a 2-count gap between the two ranges. However, the FPGA has an on-board PLL -- you can multiply the reference clock by just about any factor you like. Increase it to, say, 160MHz and you get a much better margin (though your transition rate is still limited to the speed of the RAM and the master clock). If you wanted to write back to the drive, you'd need to handle precompensation, which would involve increasing the clock rate (the ST412 and ST506 precompensation value is 12ns according to the OEM Manual). Unless, that is, you were trying to build a Write-Only Memory... :) -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/