I was hoping to share my pain with others as a coping mechanism. :)
Has anyone else worked with DRAM memory controller implementations
within FPGAs?
I have been struggling for a couple years to find a workable solution in
a hobby environment, first on Xilinx and then on Altera.
Both companies seem to push the embedded microprocessor solution,
MicroBlaze and Nios II, respectively, as an answer. They both offer a
built-in memory controller which makes access to the DRAM much much
easier, as it's memory mapped to an address region. But the problem is
that there is a certain amount of overhead associated with using the
processor both in terms of speed and logic utilization. The processors
have a maximum speed and making a "gateway" out of the processor doesn't
work for any real application.
Many people push "opencores" and say there are 30 or 40 open source
memory controllers without realizing that all of the limitations
eliminate 99% of what's out there, including:
Controllers designed for a particular memory architecture/chip type/ bus
width
Custom busses that aren't documented
Some just don't work
Require a specific vendor + FGPA because they use proprietary built-in
hardware
and so on.
There are commercial solutions which cost way too much $$$ and often
have advanced features which complicate use for the average hobbyist.
I need something that has a FIFO-like(or maybe sram-like) interface on
it, and that supports single data rate SDRAM. Something simple.
Anyone else run into problems with getting a working memory controller
for your projects?
Thanks
Keith