microcode store (was Re: Looking to get into a MiniComputer...)

On 07/30/2014 11:13 AM, Dave G4UGM wrote: Out comes the Red Book (Principles of Operation): Under "Read Direct": "The direct-out lines of one CPU may be connected to the direct-in lines of another CPU, providing cpu-to-cpu static signaling. Further, the write-out signal of the sending CPU may serve as the hold signal for the re- ceiving CPU, temporarily inhibiting a READ DIRECT when the signals are in transition. Equipment connected to the hold-in line should be so constructed that the hold signal is removed when READ DIRECT is performed. Absence of the hold signal should correspond to absence of current in such a fashion that the CPU can proceed when power is re- moved from the source of the hold signal." Basically, yes, it's a parallel port with handshaking a few extra bits--and apparently, everything stops during the transfer. From WD: "The byte at the location designated by the operand address is made available as a set of direct-out static signals. Eight instruction bits are made available as signal-out timing signals. The eight data bits of the byte fetched from storage are presented on a set of eight direct-out lines as static signals. These signals remain until the next WRITE DIRECT is executed. No parity is presented with the eight data bits. Instruction bits 8-15, the I2 field, are made available simultaneously on a set of eight signal-out lines as 0.5- microsecond to 1.0-microsecond timing signals. On a ninth line (write out) a 0.5-microsecond to 1.0-micro- second timing signal is made available coincident with these timing signals. The leading edge of the timing signals coincides with the leading edge of the data signals. The eight signal-out lines are also used in READ DIRECT. No parity is made available with the eight instruction bits." HTH, Chuck