68k homebuilts

Dave McGuire wrote: (somehow cctalk and cctech are both on the distribution list -- I'm taking cctech off) Heh, thank you, thank you. I designed that board, as well as two of the three ASICs on it. I later designed a replacement ASIC that combined all of them into one, and was pin compatible with one of the existing parts so the same board could be used. Forgive my ramble, as the opportunity to talk about this 20 year old product doesn't happen very often. The first year Byte magazine ran their top 10 products of the year, it was one of the winners. One ASIC, the first one I ever designed, was what LSI logic called a "structured array". It contained a 2KB RAM and about 5K usable gates. This part would be programmed with the x,w,w,h of some putative location of a character image on the 1 bpp frame buffer. It would fetch the bitmap and turn it into a normalized MxN gray scale image, although 5x7 was always what was used. Added as an afterthought, because I had a few hundred unused gates, I added the ability to rotate a 32x32 block of image. The 68020 would write 32 words to registers on the chip (really, it went into that 2KB RAM), then it would read them back out at a different address and get them rotated. By stepping through the image in the right order, you could rotate the entire image. It was considerably faster than having the 68020 do the rotation in software. The other ASIC I designed for that product was a 68020 memory controller plus vector compare logic. The memory controller had flexible timing control to allow interfacing to different types of DRAM, and also took care of parity generation/checking (optional). The vector compare logic would be loaded with one of the normalized 5x7 character images (although other sizes were permitted, software only ever used 5x7) and would be given a stream of pointers to reference 5x7 images in memory. The vector compare would compute the sum of squared differences on each image, and would save the best fit distance and an index to which reference character generated that best fit. A large part of the memory contained these reference characters sets. A hierarchical search was used to find the closest match very quickly, instead of a brute force compare each character against all reference images. Right now I'm drawing a blank what the 3rd ASIC did. It was designed by a guy named Jeffrey Soreff. This was before Verilog was widely used, so all of it was done via gate-level schematics, drawn using LSI's schematic capture program. While the ASICs were in fab, I designed the ISA card. We had no spec for the ISA bus, so I simply looked at the schematics and timing diagrams that came with one of our Compaq computers and with an early IBM PC. There was a control register that the ISA side could write to control the 68020; the ISA side could reset the 68020 and it could also raise an interrupt. There was an 8 bit "mailbox" register that both sides could read or write. Both sides could also read and write the DRAM on the board, although on the ISA side only an 8KB window was visible at any time, selected via a mapping register. One very interesting and touchy part of the design came from the marketing dictate that there be no user configuration jumpers on the card, which was nearly universal at the time. Instead a very elaborate configuration sequence was used; I contributed some of the ideas, but most of the hard work of making it reliable fell to a guy named John Taves. I described how it worked on this list a few years ago; in fact, I see it was on January 31, 2005. Search the archives for that date or the text "Calera Recognition Systems" and you should find it, if you care to.