15 Nov
2019
15 Nov
'19
10:08 p.m.
On Nov 15, 2019, at 4:58 PM, W2HX via cctalk
<cctalk at classiccmp.org> wrote:
This is interesting indeed. But if someone wanted to emulate a new function with the
QSIC, would they need to be able to program in verilog (or fpga language)? I think an
interesting angle using something like a BBB is that there is probably a range of
languages that could be used to implement functionality. I don't know how many people
know how to program an FPGA (or maybe a lot of peope do, but just not me :)
73 es GUD DX Eugene W2HX
Speaking as a software guy who's gotten into this stuff: it isn't all that hard.
It does require learning a new language (Verilog or VHDL; I picked the latter). And it
requires learning a somewhat different mindset. Instead of writing sequences of actions
where most of the time you have just one thread, you're describing all the things that
all the building blocks can do as they react to inputs. Also, you have to learn that
outputs don't instantaneously appear as inputs -- VHDL calls these "signals"
and models the fact that they don't become visible until the next simulation cycle.
There are simulators around that let you run VHDL (or Verilog, I assume, but I haven't
done that). Some are open source -- look at GHDL. I've used that to create quite
large models (including parts of a CDC 6600).
In other words: give it a try. You might like it.
paul