6 Sep
2006
6 Sep
'06
6:30 a.m.
Subject: PDP-8m Console Switch Problems
From: Don North <ak6dn at mindspring.com>
Date: Wed, 06 Sep 2006 01:11:51 -0700
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Cc: cctech at classiccmp.org
*****some snippage done....
Of the front panel switches, DEPOSIT, EXAM, CONT all
work fine.
The CLEAR, EXTD ADDR LOAD, and LOAD ADDR switches are nonfunctional.
What I see is strange behavior in the debounce circuit, and in fact
the debounce circuit itself is one I have never seen before (and IMHO
the designer should be hung by his entrails).
In ASCII art, here is a synopsis of the circuit:
+5V +5V 1/6*7404
| 1/4*74S175 | |\
/ +-----+-----+ | \ to
470 \ GND--| Dn Qn |------| >O-----9318
ohm / | | | / priority
\ GND--|>Clk QBn |O--+ |/ encoder
| | | |
+-------------o| MR~ | |
| +-----+-----+ |
| | |
__O ADDR GND |
O-/ LOAD |
| O------------------------------+
|
+----+
|
__O XTND
O-/ LOAD
| O---------->QBn...
|
+----+
...
|
__O
O-/ DEPOSIT
| O---------->QBn...
GND
If you understand TTL and specifically TTL FFs then this is both
logical and sane.
Most NON-BUFFERED (74x74, 74x174, 74x175) D-FFs the output is fed back
to the opposites input so any overload or transient to ground or Vcc
(not safe for device) at the output will affect the devices state.
Obviously if either output is "forced" to a state the other will follow
inverted. The caveat is if either input cannot change due to internal
failure or external logic failure the state will not change but you
may see pulses when it tries to change.
Pulling to ground is is safe as the output current (top transistor)
is limited where the lower transistor can conduct hard.
Unorthodox looking but, completely legit. You would get the same effect
using a pair of (two from) inverters (7404 for example) cross coupling
them and putting a switch across the outputs to debounce the switch.
Bottom line is it worked for 30+ years and something else is broken.
Now one of the things I've seen with older TTL is inputs that are stuck
(likely ESD or other on die failure) to either Vcc or Ground. This could
be either the '174 or the gate/inverter they drive is failed this way.
I've replaced the top 74S175 device (originally a
Signetics 74S175
date code 1970) with a socket, and have tried other 74x175 parts
but none work at all (NAT 74LS175 1983, TI 74AS175 1986, SIG 74S175
1984, TI 74175 1974). Even on the bench in a proto board I can't
get any of these devices to behave like the original. Yanking the
QB~ output to hard ground does not force the Q output high. So
was DEC relying on the aberrant behavior of a 1970 Signetics 74S175?
No, I've done this with TI, Signetics, National and others.
I'm about ready to rip out the two bogus '175s
and replace them with
some other logic (three '00s if I calculate correctly).
Anybody have any other ideas on what to look for or at?
Check the down stream logic for stuck inputs. When I repaired my 8f
(1973 manufacture date) I had several gates with the inputs stuck
(the driving gate was ok) where the input was hard high or hard low
at the pin and it was the gate itself not driving logic at fault.
A milliampmeter confirmed one gate (7400) with pin 1 hard to VCC
(Iol was >100ma). Drove me nuts as the first part replaced was
a 7474 driving that gate with no fix!
I'd give the 7404 the hairy eyeball! A quick test is socket a '175
with the Q and /Q output pins floating and using a jumper to ground
make it flip [It WILL NOT IF MR/ is asserted, you can bend out the
MR/ pin to avoid that.]. Then test the '04 for input changes output.
Allison