UNIBUS <-> PCI bridge

Hi Jochen, Do I? I don't even know what you mean! I would map the entire 18/22 bit address space into the PC address space. From a PC point of view, the complete Unibus address space will be visible with a certain address offset (defined by the PnP Bios and friends, who assign the addresses). The Unibus side will not be able to look into the PC. But.... see nex paragraph. What about simply some memory on the Unibus (I don't mention Qbus for saving keypresses)? Everything on the Unibus can see memory on the Unibus. And the PC as well. That makes thinks quite easy. Yes, there is a performance impact this way because your Unibus peripherals cannot copy their data *somewhere* into the PC address space. But I simply don't mind :-) The Unibus memory could also be integrated into the controller. That would probably that what you call DMA bounce buffer. But that's no black magic, I suppose. As stated above, I will luckily live without :-) When I read a block of data from a device, the device *slowly* fills a buffer somewhere it can see. Then I take it out. I don't mind the time I need to pull/push that data. With a fast buffer, the PC can initiate a new transfer, service the buffer, and wait for hours until the next portion of data has been processed by the Unibus peripheral! Hm. Of course. The interrupts could be directly passed on to the PC. But for the vectors, there must be built a small interrogation circuit. But... Every FPGA you can buy today has more capacities than it needs to do all that, even more, and containing a complete VAX implementation plus a pdp11 plus a pdp8.... Yes, that's a good idea. Must get a card that can interface to both. The rest is software. Best wishes, Philipp -- http://www.hachti.de