25 Jul
2016
25 Jul
'16
9:34 a.m.
On Jul 25, 2016, at 12:19 PM, Chuck Guzis <cclist
at sydex.com> wrote:
On 07/25/2016 02:31 AM, Peter Corlett wrote:
The point is that instructions that set condition codes have two outputs: their output
register, and the condition code register.
That creates both software and hardware complexity. Software complexity in the compiler,
which has to track the assignments to both these outputs and do instruction rearranging
accordingly. Hardware complexity, because the instruction issue logic has to issue the
instructions for the correct outcome in both these outputs.
paul
Eliminating condition codes just moves the
complexity from the ALU to
the branch logic (which now needs its own mini-ALU for comparisons),
and there's not much in it either way. Where it *does* win is that
the useful instructions are all single-output and so one can use the
noddy code generators found in undergraduate-level compiler
construction textbooks such as the Dragon Book.
Sorry, I'm not following this bit. I am speaking about a three-address
ISA here, BTW.
Simply adding a flag to each register reflecting its zero/nonzero
content should do the job. The high-order (sign) bit is the only other
bit necessary. Branch instructions need only inquire if either, neither
or both flags are set.
I suppose that one could also have several flags registers, being set
selectively as dictated by a field in the instruction.