PDP-8 on FPGA project & where is Hans Pufal?

Vincent Slyngstad wrote: ARGGG!!!!!! **WORMS** Check bitsavers for the hardware manuals for the PDP-8 and the PDP-5 lots of detail in what happens. The problem as I see it is that you are thinking the PDP-8 can have any memory thrown at and it works for realistic state emulation. All the computers of that era is based on the memory cycle of *CORE* memory. <setup address><read><pause><write back> Untill you design your memory around that you will have problems. The PDP 8/e's clock was I think 20MHZ to generate the proper timing for 1.2us memory cycle, I think you could just get by with 5 or 6 clocks per memory cycle. The tricky part is that Memory buffer register is latched with the core data, and then incrimented on the *same* clock. A 100 MHZ FPGA could endup at 20 MHZ but that really depends on the speed of the block ram. Ben.