24 May
2007
24 May
'07
10:08 p.m.
More seriosuly, I was once sort-of involved in a piece
of digital
design, and there was some combinatorial block that took in 3 bus
lines and outputted an enable signal to a buffer chip. Without even
thinking about the problem, I said 'I can do that in one chip'.
OK, which chip was I thinking off?
Depends. What levels did those three bus lines have to be to generate
the enable? If they're all high or all low, a three- (or more-)input
AND/NOR or NAND/OR (depending on whether the active level of the enable
is high or low).
If not, you could do it with an 8-to-1 mux with the inputs tied to
fixed levels, but it seems rather wasteful - this does, however, have
the advantage that you can run the inputs out to 8 jumpers and let the
user jumper the thing to appear at any desired subset of the 8 possible
places...or maybe that's a disadvantage; it depends.
For most combinations, you could do it with a quad NAND or NOR, but I'd
have to look at it exhaustively to be sure that's true for all eight
possibilities.
Also relevant is whether glitches are tolerable: is it acceptable for
the enable line to go active for a nanosecond or two in the presence of
certain transitions on the inputs that never actually include the magic
combination? If not, you have to make sure all the delays work out
properly.
I don't recall the numbers for any of the above chips even for the 74xx
family (which is the only one I know well enough to know those for).
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