ISA bus throughput

Good, I'm learning a bit here .. The superIO controller card I stuck in there did not look like it had a BIOS ROM extension, so I'm assuming that the chipset emulated whatever the hard disk interface was on the AT, and that the built-in BIOS on the AT is still driving everything just as though it was the original controller. It's hard to believe it is this simple, but I'm not going to argue. I never considered IDE elegant until now .. Chuck - you mentioned that the superio controller card would have a BIOS extension. Are you certain? One card that I tried definitely did, as it had the intelligence to handle larger drives. The particular card that I used does not have any options for setting a BIOS ROM address, doesn't put a splash message up at boot time, and doesn't have anything that looks like an EPROM on it. (Even though it looks quite elderly.) Eric Korpela's note indicates that it behaves more like my description above ... Another part of the equation is the CPU. If it's doing the I/O doing a tight loop, it has to be fetching instructions from memory for the instruction loop as well as doing the I/O to the bus. I was thinking that if each instruction takes a few cycles that even the tightest of loops would waste a lot of cycles, but I found a gem in the 286 user's guide - REP. Apparently you can use REP INx and REP OUTx instructions to generate a tight loop that doesn't require subsequent instruction fetches until the loop ends. So that would allow a 286 to push the bus much harder than an 8088/8086 class machine would. (The 8088/8086 would have to keep fetching instructions, which would suck.) Mike