Unibus disk controller with modern storage

On Wed, Oct 19, 2016 at 4:48 PM, shadoooo <shadoooo at gmail.com> wrote: True. From a Chinese vendor such as PCBway, a DEC quad size double-sided PCB without ENIG (immersion) gold surface finish but without hard-gold edge fingers costs $15.10 each in quantity 10, and a hex side PCB costs $20.40 each. However, the ENIG gold is quite thin and won't withstand very many backplane insertions. The cheap PCB vendors don't offer hard gold edge fingers. Jon Elson pointed out that E-TekNet in Arizona does offer hard gold at better prices than some fab houses, but still a lot more than the cheap Chinese PCBs. I prefer NOT to use ENIG, as I find HASL tin-lead better for hand assembly, though the lead is a problem due to RoHS regulations in much of the world (but not in USA). I haven't tried HASL lead-free. Xilinx XC6SLX9-2TQG144C is probably big enough for such things, and only costs $16.52 in quantity 1 from Digi-Key. It's in a TQFP, so not *too* difficult to deal with. It has essentially 11,440 logic cells (5-LUT with FF)*, 32 block RAMs of 18 Kbits each, and 102 3.3V I/O pins. It's not 5V tolerant, but no modern parts are. 5V tolerance can be achieved in many cases by the use of series resistors, but I like using the TI SN74CBTD3861DGVR bus switch/voltage clamp, which can make 10 I/O pins 5V tolerant at a cost of $0.62 in quantity 1. The bus switch is advantageous over series resistors because it doesn't add much series resistance to pins that are being used as outputs, and it has a maximum propagation delay of 0.25ns. If you need more FPGA capability, the XC7A15T-1FTG256C has substantially more resources, and costs $25.69 in quantity 1. It's in a 256 ball BGA, so somewhat harder to deal with, and needs at least a four layer board, possibly even six layer. However, it has 20,800 logic cells (5-LUT with FF), 25 block RAMs of 36 Kbits each, and 170 3.3V I/O pins. If you need more resources than that, it turns out that the XC7A15T, XC7A35T, and XC7A50T are actually all the same die, just factor-programmed with a different device ID. The 35T and 50T have double and triple the logic cells and block RAMs of the 15T. The Vivado FPGA toolchain artificially limits the resource usage of the two smaller parts, but doesn't actually restrict which specific logic cells and block RAMs are used, which means that the 15T and 35T have silicon that passes the factory testing for ALL resources, not just 1/3 or 2/3 of them. It's been verified that one can change the device ID in the bitstream, disable bitstream CRC checking, and use the smaller part as a larger part. I don't like disabling the CRC, because it serves to protect the FPGA from damage if the bitstream has been corrupted, so I wrote a program that can both change the device ID and recompute the CRC. I don't yet have a board with a 15T or 35T to test with, but I'll release the program as open source once I do. Because going to a 4 layer or 6 layer board is quite expensive when the board size is large, e.g., DEC quad or hex size, I think it makes sense to put the FPGA, its configuration flash, voltage regulators, and the bus switches for 5V tolerance on a daughterboard. I've been working on such a design, with two 96-pin DIN connectors for connection to the main board, and at least 160 GPIOs available. The main board can then be just double-sided, and possibly even 100% through-hole, for people that don't want to hand-assemble boards with surface-mount components. The drawback is that it will occupy more than one backplane slot due to the height. There's still the problem that no current production bus interface ICs meet Unibus, Qbus, or Omnibus specifications. Surplus DS8641 chips are technically the best choice. With modern chips, it's necessary to use separate drivers and receivers, and still difficult to meet the full specs. Compromising the specs is possible but may make things unreliable in a large system (multiple backplanes with cables, and many other cards). Eric * Xilinx has some other confusing definition of a "logic cell" for marketing purposes, which is not the same as a LUT+FF. Oddly enough, their marketing logic cell count is actually lower than a sensible accounting, which is the opposite of how FPGAs used to be rated in exaggerated gate counts, which we derided as "marketing gates". The 6-series and 7-series actually have 6-LUTs with 2 FF each, but they can be used as two 5-LUTs with 1 FF each, which is how I count them for assessing the FPGA's logic capacity.