Sorry for the late reply.
Brad Parker wrote:
On Mar 11, 2010, at 2:33 PM, Philip Pemberton wrote:
And this
is my current frustration! Verilog. FPGAs. Etc.
Verilog isn't that hard to
learn, it's all the other stuff that goes along with it (metastability, clock
synchronisation, clock domains, finite-state machine implementation, ...)
It's a good point. If you want to make reliable designs you need to learn and
understand all those things very well.
If you want to do real synchronous design, which most of these fpga or even cpld designs
should be,
you need to learn some fundamentals. As painful as it might be, I'd try and find one
of the entry level
EE logic design courses, either on the web or via a book.
Yeah, I think the one problem is that I'm trying to learn logic design
AND verilog at the same time. I've got some basic skills but they are
definitely falling short.
When you talk about courses via the web, are you referring to stuff like
MIT's OCW, or ?
An EE friend of mine used "Contemporary Logic Design", and it looks like
the book is available used for cheap. I flipped through it, it seems
decent enough. Any other recommendations?
But you really need to learn proper state machine
design if you want your designs
to work in real hardware...
The language templates within xilinx's ISE provide a number of example
state machines. I've used their basic outlines, and then watched the
synthesis process to ensure that the state machines were being extracted
and recognized in my projects.
check out "Verilog Digital Computer Design:
Algorithms Into Hardware". It has a lot of examples you could
type in and get to work quickly.
Is this by Mark Gordon Arnold from 1998? I always wonder about older
books. If they are the defacto reference standard, it's one thing. I
sometimes think that if they are generic enough to still apply, it's not
specific enough to my boards/environment/current language standards to help.
If I'm working on classic computer stuff, then much of material is old,
so then the associated books are old too.
In the end, verilog is just the tool. You'll need
to understand good digital design viscerally but once you do you
can use any HDL - they're all the same in the end.
Thanks
Keith