23 Jun
2007
23 Jun
'07
7:10 a.m.
Subject: Re: Re: T11 design WAS - Re: Inside old games machines, was: Re:,Simulated
CP/M-68K?
From: Johnny Billquist <bqt at softjar.se>
Date: Sat, 23 Jun 2007 02:43:26 +0100
To: cctalk at classiccmp.org
Allison <ajp166 at bellatlantic.net> skrev:
No, it isn't. Where did you get that? (And I've just triple checked my
memory by actually reading through parts of the 11/40 and 11/70 manuals.)
The 11/70 don't even have a read-modify-write cycle defined on the
memory bus. If you write less than 32 bits, the memory box itself must
do the read-modify-write cycle. The CPU and memory bus is totally
unaware of that detail.
On the Unibus, the processor can use both pure write cycles (DATO/B) or
read-modify-write (DATIP followed by DATO/B).
Then why is the output address of a DL card differnt from the input
address? It doesnt have anthing to do with the read before write
does it?
> >
> >Subject: Re: T11 design WAS - Re: Inside old games machines,was:
Re:
Simulated CP/M-68K?
> > From: "Ethan Dicks"
<ethan.dicks at gmail.com>
> > Date: Wed, 20 Jun 2007 16:22:25 -0400
> > To: "General Discussion: On-Topic and Off-Topic Posts"
<cctalk at classiccmp.org>
>
>On 6/20/07, Roger Ivie <rivie at ridgenet.net> wrote:
> >> On Wed, 20 Jun 2007, Allison wrote:
>> >> > It's an easy cpu to interface and use...
>
> >>
> >> However, it's not without its obnoxious bits.
> >>
> >> On the T-11, all writes are performed as read-modify-writes.
>
>Hmm... was that because of the needs of core memory, or was it just to
>simplify some aspect of its internal design?
It's part of the memory to memory design and the way intructions work.
It's annying as micros go but ALL PDP-11s word that way and the T-11
is a PDP-11 in LSI. The memory systems can, and must be able to deal with
both. Saying that
RMW is a part of the memory to memory design is pure nonsense. And the
same for how instructions work. It depends on wether the instruction
mandates that it's a RMW or not.
Arithmentic instructions for instance, are typical read-modify-write,
while pure writes becomes pure writes on the bus to memory as well.
Ok, You attacked me. Why does the T-11 and most all of the Qbus
machine do a read before write, or as you say a DATIP before
any DATO(B/W)?
So in short: writes on PDP-11 systems in general
don't imply a read.
That's a T-11 thing if it does, and is probably related to simplifying
the design (internal) more than anything else. I don't think they did it
with core memories in mind. All Unibus core memories have their own
write-back. That isn't something the CPU bothers with.
For the Q-bus, I don't even know if any core memories exist.
I do as I have two 16k sets (32kW).
Allison
Johnny