26 Oct
2016
26 Oct
'16
6:39 a.m.
Guy S.
Thanks saved me the time to say exactly what you said. For all those that
thing designing a driver is a simple thing to do, make your self a
simulated Unibus that is 50 feet long, add around 30 'stubs' load it down
to the max and show me your 'easy to build' drivers signal quality.
On Mon, Oct 24, 2016 at 11:13 AM, Guy Sotomayor Jr <ggs at shiresoft.com>
wrote:
bus by
inserting or removing
The biggest concern is when interfacing to UNIBUS. In the PDP-11 UNIBUS
Design Description
document on Bitsavers, page 4-1 indicates what the Unibus interface chips
are and what are *not*
recommended (8640, 8641 and 8881 are the only ones recommended).
There are a number of rules that must be adhered to when building out a
Unibus system. These
include:
Maximum cable length must be < 50?
Maximum DC loading < 20
Maximum lumped loading < 20
There are rules where cable lengths must be *increased* to avoid
reflections.
A single Unibus can be divided into multiple segments. Each segment must
adhere to the above
rules, so you can see that a Unibus can be quite large.
For example, my PDP-11/40 resides in 2 BA11-F boxes (23? tall) and are
fully populated with
Unibus backplanes (5 9 slot backplanes each) with a BA11-15 (15? cable)
connecting the two.
My point here is that the Unibus has a very different electrical
environment than Q-bus or Omnibus
and what may work for them will probably have troubles on a Unibus.
TTFN - Guy
On Oct 24, 2016, at 10:37 AM, allison <ajp166
at verizon.net> wrote:
On 10/23/16 2:59 PM, Al Kossow wrote:
>
> On 10/23/16 11:50 AM, shadoooo wrote:
>
>> The problem is that there aren't open drain bus transceivers, but the
>> problem could be solved simply using input-only and output-only
components,
>> connecting two in parallel but opposite
direction on bidirectional
pins.
>>
> The reason for using the old parts is the logic thresholds are unique to
> the Unibus to handle worst-case bus loading and the termination voltage
they
used.
The voltages are based on TTL levels. What are the unique voltages?
The key was limited leakage current and input current to not load the current from a node (there is a specified maximum
in per node and total
nodes). That cover input
to card devices and bus driver leakage.
Logic low voltage is typical of TTL and the driver device has to sink
that current
and meet that value.
Logic High was set by the terminator devices at
3.36V but the threshold
is lower based on the bus
receivers.
By late 1970 it was an easy spec to meet, When first used (pdp8e) it
was new and
the ICs
were not so great with leakage current and output
device saturation
current.
Every time this comes up the world is supposed to stop if not met. The
LSI-11 bus
(qbus)
was actually harder as it was 120 ohm terminated
and HeathKit did it
with common TTL
and the CPU was DEC standard LSI-11 and it worked
out to 18 slot
backplanes.