Fairchild 9401 ttl ic pinout wanted.

Philips/Signetics second-sourced it, and I have the datasheet in front of me. There's also the Signetics 8X01A, which is similar, but with the extra feautre of beign able to do the SDLC-specificed patern match. It's a fairly common device in old discrete-ish logic disk controllers Anyway, here's a pinout and some notes 1 : CP/ 2 : P 3 : S0 4 : MR 5 : S1 6 : N/C (Pattern Match Enable on 8X01A) 7 : Ground 8 : S2 9 : N/C 10 : CWE 11 : D 12 : Q 13 : ER 14 : Vcc Where : CP/ = Clock Pulse Input (falling edge triggered) D = Data input Q = Data Output CWE = Check Word Enable. basiucally. this is held high while data bits are applied to the D input, the polynomial value is calculated in an inteernal shift register. Then CWE is taken low and the contents of this regiser shifted out on the Q output. MR = Mater Reset P = Presett (polynomal register to apporpriate value) ER = Error flag output S2...S0 = Polynomial select inputs. Reading these as an octal digit (S2 is the MSB), the polynomailas are : 0 : X^16 + X^15 + X^2 +1 (CRC-16) 1 : X^16 + X^14 + X + 1 (CRC-16 Reverse) 2 : X^16 + X^15 + X^13 + X^7 + X^4 + X^2 + X + 1 3 : X^12 + X^11 + X^3 + X^2 + X + 1 (CRC-12) 4 : X^8 + X^7 + X^5 + X^4 + X + 1 5 : X^8 + 1 (LRC-8) 6 : X^16 + X^12 + X^5 + 1 (CRC-CCITT) 7 : X^16 + X^11 +X^4 +1 (CRC-CCITT Reverse) Hope that helps. There's not much more in the data sheet other than tables of timeing and electical characteristics, which you probably don't need. -tony