11 Apr
2015
11 Apr
'15
12:25 a.m.
On Sat, Apr 11, 2015 at 12:58 AM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
Coincidentally, I'm working on a Wang 520 right
now, a descendant of the Wang 700 Rick mentioned, which uses a 2048-word * 42-bit core
rope ROM for the microcontrol store. There can be over 1000 or 2000 address lines going
through a given core.
That is amazing! The core rope memory systems I've read descriptions
of have used far fewer addresses per core. For a 2Kx42 ROM with 1K
addresses per core, that would only need a maximum of 84 cores (and
perhaps only 42 if the distribution of ones and zeros was uniform
enough for each bit of the word), but they'd have to be fairly large
cores. I'd have expected it to be more cost effective for manufacture
to use a much smaller number of addresses per core, which would allow
use of smaller cores, ease the manufacturing, and probably have better
SNR of the output pulses. However, I'm sure the engineers at Wang knew
far more about it than I do, so they undoubtedly chose the most
cost-effective design that met their reliability objectives.