26 Jan
2011
26 Jan
'11
12:29 p.m.
On 1/26/2011 1:48 PM, Philip Pemberton wrote:
On 26/01/11 18:19, Keith M wrote:
I guess that's what I mean. :)
My chip is actually a
A3V64S40ETP is organized as 4-bank x 1,048,576-word x 16-bit Synchronous
DRAM with LVTTL interface.
http://www.zentel.com.tw/download/A3V64S40ETP_v1.1_Zentel.zip
(sorry for zipped pdf)
which seems to have similar specs to a more common
http://www.issi.com/pdf/42S16400.pdf
Has anyone else worked with DRAM memory
controller implementations
within FPGAs?
If you mean single-data-rate PC100 SDRAM, then yes. Ended up rewriting the stupid thing... I started from
the ground up,
eliminated the concept of caching reads/writes (I wanted this for a CPU
core which already had an Icache and Dcache built in), and went for the
"simplest option". Took me about three days to get it working and
properly parameterise the Verilog code.
You can change (at build time):
Data bus width (link to CPU)
Number of SDRAM column address bits
Number of SDRAM row address bits
Number of SDRAM bank address bits
CAS latency
T_rp, T_rcd, T_rfc, refresh rate, initialisation delay and time before
enabling CKE
Jeez. That's pretty good if you can write a dram controller from the
ground up in three days. It took me longer just to get Xilinx's MIG
controller to synthesize.
None of these are adjustable at runtime; that's
been on my TODO list for
about six months. Ideally I want to add a control bus to it, which will
allow the host to change the SDRAM timings as required. I'll probably
need this if I ever want to tie it to a PC SDRAM DIMM.
This "high performance dram memory controller" (hpdmc) has been modified
to work with my memory.
https://github.com/marmolejo/zet/tree/master/cores/hpdmc_sdr16/rtl
It has a control bus and a data bus based on FML("wishbone w/o the
corner cases"?)
http://www.milkymist.org/socdoc/hpdmc.pdf
You can't really adapt SDRAM to an SRAM type
interface because of the
way SDRAM is addressed. If you're already in the right bank and row,
then you're more or less fine. If not, then you have to do a bank select
and row precharge. That takes a couple of clock cycles to kick in, so
you need to tell the host to wait a little while before reading the data
bus.
Maybe not adapt per se, or directly convert, but certainly you could
have an easier to use interface.
Like maybe front-end a small FIFO to the memory controller. Keep
checking the FIFO depth, and read when necessary. There's no
requirement for instant data from the controller.
I guess I should have said "present an easier to use interface" instead
of an "sram-like interface."
Thanks
Keith