11 Aug
2008
11 Aug
'08
4:46 a.m.
Pete Turnbull wrote:
On 11/08/2008 07:37, schwepes at moog.netaxs.com
wrote:
<nitpick>
This doesn't look correct. My 8008 8 bit parallel CPU manual gives the
following order on the data bits. (Also at bitsavers at
http://bitsavers.org/pdf/intel/MCS8/8008usersManualRev4_Nov73.pdf )
8008
__ __
(-9V) Vss | U | INT
D7 | | READY
D6 | | phi1
D5 | | phi2
D4 | | SYNC
D3 | | S0
D2 | | S1
D1 | | S2
D0 |_____| Vcc (+5V)
</nitpick>
And to answer another question about the screen on the Datapoint 2200,
it was 12 rows of 80 characters.
Btw, anyone have an Intellec 8 computer they don't need? It's one of my
"wish list" machines. :-)
/G?ran
The 8008 was only introduced a year after the
4004 which was
introduced in 1971. I can't find a pin out for either of them
but I suspect that they might be pin compatable so that the
upper four bits would be simply not used if the 8008 was put
in a system designed for a 4004.
Not even close, I'm afraid. The 4004 is a 16-pin device with Vdd
(-10V) and Vss (+5V) on the centre pins of the two sides, the 4 data
bits on pins 1-4, and the two clock phases and SYNC on pins 6-8. The
8008 is an 18-pin device with Vcc (+5V) and Vss (-9V) on diagonally
opposite corners (pins 1 and 10), D0-D7 on pins 2-9, and the clock
phases and SYNC on the other side (pins 14-16):
4004 8008
__ __ __ __
D0 | U | CMRAM0 (-9V) Vss | U | INT
D1 | | CMRAM1 D0 | | READY
D2 | | CMRAM2 D1 | | phi1
D3 | | CMRAM3 D2 | | phi2
(+5V) Vss | | Vdd (-10V) D3 | | SYNC
phi1 | | CMROM D4 | | S0
phi2 | | TEST D5 | | S1
SYNC |_____| RESET D6 | | S2
D7 |_____| Vcc (+5V)