29 May
2014
29 May
'14
2:36 p.m.
On 5/29/2014 11:15 AM, Rich Alderson wrote:
From: Henk
Sent: Thursday, May 29, 2014 1:13 AM
SIMH seems to limit XCT nesting to 32. It also limits indirect effective
address nesting to 32.
I don't seen any limitation for this kind of nesting in the KS10
microcode and the indirect effective addressing doesn't look to be
interruptable.
Rob.
-----Oorspronkelijk bericht-----
From: Chuck Guzis
Sent: Wednesday, May 28, 2014 10:42 PM
> On 05/28/2014 12:50 PM, Henk wrote:
> I remember the EX (execute remote)
instruction. I wonder what would
> happen if you EX to another EX instruction that EX'd the first EX. That
> would cause a loop, I guess. But both systems that I worked on, the
> system would not hang, just the CPU executing the EX code.
I seem to recall that the S/360 had a special
exception code for an EX
instruction being the object of another EX instruction.
I have no access to SPERRY documentation, but I
would expect
that the 1100 also would recognize EX targeting an other EX and
generate an exception or trap. IIRC the word is 'contingency' in the
1100 jargon for 'exception'. End 80's memory cells starts to fail ...
On the other hand, the PDP-10 architecture explicitly allows an XCT as the
argument of an XCT, so the looping scenario is possible. However, the
interrupt system should allow the system to break out on a time-slice
expiration, so only the individual process should hang.