23 Aug
2019
23 Aug
'19
7:05 p.m.
On 08/23/2019 12:47 PM, Noel Chiappa via cctalk wrote:
Right, but the idea is to schedule memory reads way in
advance of when the datum is required for a calculation.
So, the load from memory to register is moved way up in the
program, and the use of the register is much later to allow
for the memory latency. Yes, it is not exactly like drum
memory computers, but you are still scheduling things for
when they can be done without causing a stall.
Jon
From: Jon
Elson
> On 08/22/2019 12:47 PM, Tom Uban via cctalk
wrote:
> On a possible related note, I am looking for
information on converting
> CISC instructions to VLIW RISC.
I think it might end up looking a bit like the
optimizers that were
used on drum memory computers back in the dark ages.
I dunno; those were all about picking _addresses_ for instructions, such
that the next instruction was coming up to the heads as the last one
completed.