31 Oct
2010
31 Oct
'10
10:54 a.m.
On 31 Oct 2010 at 8:21, Jerome H. Fine wrote:
Interesting!! I worked for CDC in Toronto from around
1972 to 1977 on
the local PL-50 program. IIRC, the PL-50 was a much slower version of
the STAR-100, but with the same instruction set. Initially, the goal
was to write an operating system.
I was part of the Sunnyvale mafia and worked with quite a number of
your Canadian co-workers. Anil and I later partnered up on the
FORTRAN compiler for the ETA-10. You probably remember that the PL-
50/STAR-65 met an unfortunate fate at the hands of the corporate
"leave nothing behind" people. I witnessed firsthand, the
destruction of the two STAR-1B systems a couple of years later. It
wasn't pretty--a dumpster, bolt cutters and large hammers. I saved a
heatsink from the power supply--there wasn't much else left intact.
I begged to be allowed to take the ROS stack from one system, but no
such luck. The stations were removed and sent back to Arden Hills.
--
I'm going from memory on this one, but there's some STAR literature
on bitsavers if you want to check my facts.
256 registers of 64 bits; if halfword mode was selected, the lower
128 were doubled and the upper 128 were inaccessible. Many registers
had special meanings, including program status, cycle timer and a few
others.
Internally, memory was fetched 512 bits ("Super word" or "sword";
really 544 bits with ECC included) and the vector pipes were 128 bits
wide (2 single-precision results per cycle).
An odd machine in that scalar operations were most decidedly RISC in
attitude. For example, there were only load and store register-
memory operations and one had to use 2 instructions (EX and ELEN) to
enter a full 64-bit immediate constant into a register. No stack or
auto-increment/decremet per se; subroutine linkage was done with a
sort of S/360-style LM-STM combo "swap" instruction that
simultaneously stored and loaded any number of registers. The
machine architecture itself was basically 3-address, so instructions
were either 32 bits or 64 bits in length.
Before an ECO ("Rev. R") was installed on all systems, all registers
could also be addressed as the lower 256 words of user memory address
space. This hugely complicated instruction scheduling and so it was
determined that it wasn't needed.
I know you guys used the RED OS, but we had to use STAR-OS from LLL
as our base in Sunnyvale. It was basically a message-passing OS with
a controller started by the job scheduler, which could have as many
controllees as desired. You could send a message up the chain, one
level, or to the top or broadcast to all controllees. I recall that
the termination message content was the characters "ALL DONE".
Regarding paging, I saw my share of DEADBEEF codes (was the STAR OS
the first to use this failure code?). At some point we went from a
demand-paging algorithm to a working-set one, but the stuff that the
pager had to keep track of made the code a nightmare. Jim Smith
suffered a lot on that thing. It didn't help that we had to scavenge
time on the customer systems at LLL or hop the "noon balloon" out of
San Jose to use the system at ADL.
One thing that I never got to try on the 100 was seeing how long a
maximum-length packed BCD divide would take. Given that the byte
instruction field lengths were 16 bits, it meant either 65K or 131K
digits...
One memory I have is being sent to Arden Hills in January during the
OPEC oil embargo and settling in for the night in the machine room at
ADL because it was warmer than my room at the Ramada.
I"d love to find someone who spent time on the TI ASC to compare
notes...
--Chuck