25 Jul
2016
25 Jul
'16
2:31 a.m.
On Fri, Jul 22, 2016 at 11:59:59AM -0700, Chuck Guzis wrote:
[..]
Something that's always bothered me about
three-address architectures like
ARM is why there is the insistence on that scheduling bottleneck, the
condition code register? You can see how two-address architectures like the
x80 and x86 try to get around the problem by having certain instructions not
modify certain condition code bits and even have specialized instructions,
such as JCXZ, that don't reply on a specific condition code.
Anyone have a clue?
The condition code register can be treated as a regular register that partakes
in register renaming. Effectively, you have *many* CCRs in flight, so only
*reads* of the register may cause stalls. These reads are usually branches, so
there's branch prediction caches to try and deal with those stalls.
Unsurprisingly, the x86 ISA is brain-damaged here, in that some instructions
(e.g. inc") only affect some bits in EFLAGS, which causes a partial register
stall. The recommended "fix" is to avoid such instructions.
Eliminating condition codes just moves the complexity from the ALU to the
branch logic (which now needs its own mini-ALU for comparisons), and there's
not much in it either way. Where it *does* win is that the useful instructions
are all single-output and so one can use the noddy code generators found in
undergraduate-level compiler construction textbooks such as the Dragon Book.