Discferret broken?

On 02/03/12 11:04, Christian Corti wrote: That's not strictly accurate. The DiscFerret has a 50MHz four-line High Speed I/O interface. What you could do is use two lines to talk to an I/O expander (read: microcontroller) which issues commands to the drive, and use the other two for high-speed data and clock from the RS422 receivers. You'd have to modify the microcode to make it work, but that's exactly why I used an FPGA: it'll do anything you ask of it, depending on how the logic array is programmed. If you get a read-clock and a read-data line, use RDCLK to shift stuff into a high speed shift register, then every eight clocks store it in a FIFO. On the other side, use the same memory interface logic the DiscFerret stock firmware uses (the MWR fifo and address counter). When you get an index pulse, store the contents of the SR and latch the number of bits stored into a holding register. Most of the ACQCON logic would be common. The LGP30.. I'm not 100% certain I understand the drive interface so I'll refrain from commenting. Even so, I don't have access to an LGP, so testing would be difficult at best. I've no doubt that you could read it into a DiscFerret, again with a microcode change and a buffer board, but there's no reason I'm aware of which would make it impossible. "You keep using that word. I do not think it means what you think it means." :) Thanks, -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/