IBM 5150 maximum memory?

In very simple terms, if the interrupts are level-triggered, then they can be shared by multiple deivces, if they're edge triggered, they can't be. Suppose you have 2 devives A and B sharing an interrupt line. If A assertes the line, the _change_ in state of that line is the 'efge' that indicates and interrupt has occured. B then also tries to assert the line, nothing happens (the line is already asserted), but when A releases it (when it's interrupt is acknowldeged by the processor, for example), then the fact htat B is still asserting the lien will be _missed_ by the processor, since there wasn't a change of state to cause the 'edge' that the interrupt controller cirucit is looking for. On most other machines the interrupt are, iondeed, level triggered. And the fact that you only have 4 or 8 interrupt lines is not a problem because many devices can share each one. But on the ISA bus you have to have a spearate line for each device. [What possesed Intel to include an edge-triggered mode in the 8259 interrupt controller chip is beyond me too, BTW. It was asking to be misused] -tony