CPU design at the gate level

A big part of this problem is that there is such a wide range of what is collectively referred to as a processor. If you want to know how to design, at the gate level, a set of registers, you start with how to build a flipflop and go from there. If you want to consider the datapaths, you figure out what you want in the way of multiplexers and tristate busses. The remainder is in how to build a sufficiently fast ALU, and how to design an instruction set. Most people start with the architecture, and that will dictate much of what's needed in terms of registers and data steering logic. Concatenating the datapaths in order to provide the necessary functions is not terribly difficult if the instruction-set/architecture combination is regular and well-designed. It's difficult to discuss in advance of a specific set of requirements, however, because each case varies considerably. I wouldn't be too hard on authors for not trying to do what can't be done well. Specific examples are widely available in VHDL and Verilog examples on the WWW. I find the VHDLs easier and quicker to understand than schematics, even though I was raised on schematics. Dick ----- Original Message ----- From: "Tony Duell" <ard(a)p850ug1.demon.co.uk> To: <classiccmp(a)classiccmp.org> Sent: Friday, September 21, 2001 7:35 PM Subject: Re: CPU design at the gate level