cpld design

Chuck Guzis wrote: Agreed. I started using Verilog because it uses C style expressions (and most of the operator precedence rules are the same), and the language structure follows similar conventions. The keywords, OTOH, are more like Pascal... This does (IME) occasionally "lead you down the garden path" sometimes. I've found myself thinking in terms of how I'd implement something in software, then realising that I was writing HDL code and describing hardware... Makes for some fun design quirks. (Thankfully I think I've eliminated most of the ones that crept into the DiscFerret disc analyser -- which is in the first stage of prototyping at the moment. I'm currently prototyping and stress-testing the power supply / voltage regulation circuitry) -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/