1 Jan
2019
1 Jan
'19
2 p.m.
On 1/1/2019 8:58 AM, Carlo Pisani via cctalk wrote:
hi
on DTB we are designing a RISC-ish CPU, code name "Arise-v2"(1).
We are using the MIPS R2K and the RISC-V as the reference.
In the end, it will be implemented in HDL -> FPGA.
The page on DTB is related to a software emulator (written in C) for
the whole system. CPU + RAM + ROM + UART, etc. so we can test and our
ISA more comfortably.
As a second reference, I'd like to consider the first Motorola RISC:
88K, which is very elegant and neat ISA; unfortunately, I have
difficulties at finding user manuals and books about it.
If someone wants to sell me a copy, it will be appreciated!
Thanks and happy new year!
I was never a fan of RISC architecture as does not fit the standard high
level language model. Everybody wants a 1 pass compiler, thus the RISC
model. If you are doing your own RISC model, you might consider a model
that supports Effective addressing better since we have got the point
where fetching the data is taking longer than processing it.
The other thought is the pipeline seems has too high speed of a clock,
what is the use a fast clock, if you got one or two gates of logic
between your clocks. Gate and line driving speed ratios remind me of
the Vacuum tube era of computing.
I have FPGA card here, as using it to develop a NICE 20 bit TTL
computer.I just ordered a few 7437's from the Ukraine, so this might be
the last year to stock up needed 74XXX spares.
Good luck with your design.
Ben.