4 Aug
2008
4 Aug
'08
3:38 p.m.
On Monday 04 August 2008, Tony Duell wrote:
The 11/03, and LSI-11/2, probably the SBC-11/21, and the 11/23 when not
fitted with an MMU. I can't think of any others off the top of my
head. :)
And, in case
you're worried that hardware had to be adjusted
depending on what address bus used, it didn't. The CPU asserts a
I/O page line on the bus whenever there's an access to the I/O page
of address space, So, the device only needs to check 12 address
lines (memory accesses are 16 bites wide) and the I/O page line,
regardless of how wide the address bus on the CPU is.
Actually, that's only yhe case on the Q-bus, which could have either
18 or 22 address lines (was there ever a version that only drove 16
address lines?) On the Unibus, there are always 18 address lines, and
devices check
all 18 of them. On machines without an MMU, or with the MMU turned
off, the top 2 address lines (A16 and A17) are asserted if all of
A13...A15 are 1's. AFAIK, that was the case from the very first
PDP11, which is the whole point of this discussion, the machine was
designed with the future in mind Unibus machines with 22 bit
addressing have a special memory bus (not UNibus) with 22 address
lines, and a second, simple, MMU, called the Unibus Map, between the
18 Unibus address lines and the 22 memory address lines for DMA.
Still, this is equivalent to how the QBUS did it, only without using a
separate line to signal I/O page accesses.
Pat
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