AFAIK, the
68LC040 in your Quadra 605 actually runs at 50MHz internally, but
on a 25MHz external bus.
Right. That's an '040 thing. Motorola never emphasized it until much
later, once Intel began hyping the DX2 line of 486 processors.
Motorola *never* emphasized it, because it's false. Unlike the 486DX2,
the 68040 does NOT run at the double speed clock (50 MHz in the
example). The pipeline stages run at the 1x clock (25 MHz). Motorola
knew that they'd get a black eye for misrepresenting it if they claimed
it was running on the 2x clock. It was *Apple* that decided to
misrepresent it in their advertising.
Another example of processors that need a clock input at a multiple
of the pipeline rate is the Microchip PIC, which needs 4x.
In these sort of processors, it is true that *something* happens on each
clock. But not that a "complete operation" takes place on each clock.
For the 486DX2, which typically ran on a 33 MHz clock and internally
generated a 66 MHz clock from that, the pipeline *does* run at 66 MHz.
This in no way reflects badly on Motorola, as they documented the
behavior correctly. It does show, however, that they were starting to
lose the CISC performance competition. Probably because Intel was
simply able to outspend Motorola on high-end microprocessor R&D.
