24 Sep
2003
24 Sep
'03
8:36 a.m.
Doc,
I'm going over the card configuration of a
PDP11/84 and reading the
online documents, and I'm confused about a couple of things. I need to
get squared away on this, as I'm testing some drives needed in
production and only have Unibus SDI adapters.
oooh. I'd kill for an UDA50.
You lucky [nastiness suppressed] :)
Unibus is a straight-through wiring, with the bus being on each slot
on connectors A and B. C-F are for the boards. So, on any given
backplane (such as a regular BA11-L 9-slot backplane), you will
have "BUS-IN" (slot 0-AB), "BUS-OUT" (slot 8-AB), and
"POWER" (the
various power connections.) BUS-OUT can be another Unibus cable
(the very wide white flatcable), or an M920 interconnect module
which sits inbetween two backplanes to bridge them together, or
anohther M-type module being the terminator (M913 I believe) of
the bus.
Sneaky detail: Unibus has DMA support, and the DMA (NPR - Non-Processor
Request) lines are wired-through. The *grant* line, however, often
gets broken by a card, to make sure cards "behind" it (on the bus)
dont grab the request. After removing such a card (the UDA50 is an
example) you have to either re-wire the NPG (Non-Proc Request Grant)
lines (on the C block, I believe) or insert an NPG-bridge card which
effectively does the same.
First, there's an expansion chassis. It has a
terminator card
(M9302) in row 7 (starting from 0) in what I assume is slots E-F (front
No, that is
AB. So, yes, the 9302 is the unibus terminator board, the
good one (with active termination.)
of the rack is A?). OK, I get that, but theres a
non-NPG single-slot
grant card in row 7 slot C, and in succeeding rows, there are more
Ahh, see above.
boards - M9700 or M9100, M105, M7226 in row 8, power
and M7821 in row 9,
power and M117 in row 10, and M002 in row 11. How is this functional?
See above
:)
Slots could be *empty*, as long as the NPG was not broken.. slots which
had their NPG broken need to be either rewired, or have a G727 in row
C to fix the NPG.
Is there a reliable way to determine grant
configuration without
physical examination of the backplane? The machine was [allegedly] very
recently running in this configuration, but I don't want to smoke
something by counting on that. I'd like to strip the non-essentials for
testing. A test setup in a single card cage - base boards plus SDI and
RX02 controllers - would save a lot of juice and reduce points of failure.
First,
run ONLY the CPU with the terminator. The 11/83 CPU board already
has console and such, so this is already a working system which displays
output. If that works, add a simple board (RX11). Then add the UDA50,
which is not simple..
Last, the CPU is an M8190-AE, which lists in Megan
Gentry's reference
as 11/84 *or* 11/83? So I could drop this pup into a QBus chassis after
the SDI drives are tested? What would be the relative merits of doing that?
The
8190 indeed is an 11/83 CPU. The PDP-11/84 system is a Unibus based
system, but with a Qbus core and a bridge inbetween- this is so DEC did
not have to do another (unibus) CPU. So, the 11/83 + Qniverter = 11/84,
which is why Megan's info is correct.
On the Unibus subject: if anyone has a UDA50 and/or RL11 and/or DELUA
available, let me know :)
Cheers,
Fred
--
Fred N. van Kempen, DEC (Digital Equipment Corporation) Collector/Archivist
Visit the VAXlab Project at http://www.pdp11.nl/VAXlab/
Visit the Archives at http://www.pdp11.nl/
Email: waltje(a)pdp11.nl BUSSUM, THE NETHERLANDS / Sunnyvale, CA, USA