2 Oct
2010
2 Oct
'10
7:45 p.m.
Dwight wrote:
Another possible is to put an incrementor on the
output.
This is a simpler circuit than a full adder.
I wrote:
> In "discrete" logic, or in an ASIC, it
is simpler. In most FPGAs, it
> will end up taking the same resources and having the same performance
> as a full-adder.
Dwight wrote:
Half area but just as long in time.
Same area
in FPGA, not half. Almost all FPGAs use LUTs with four or
more inputs, and half-adders generally end up taking a full LUT, just as
a full-adder does. The exception would be when the incrementer
(half-adders) could be merged with the previous stage of logic, but when
the incrementer follows a full-adder, you can't merge them, because they
each need a separate carry chain.
Eric