9 Feb
2015
9 Feb
'15
1:27 p.m.
On Mon, Feb 9, 2015 at 5:38 AM, Noel Chiappa <jnc at mercury.lcs.mit.edu> wrote:
The 11/45 (etc.) semiconductor memory is on Fastbus, which is attached
to the KB11-D (or -A) CPU via a memory controller. The memory
controller does have a Unibus port, but the Fastbus memory modules are
not on the Unibus any more than an RP04 disk drive is on the Unibus.
In both cases there's an intermediary to give the logical appearance
of a device on another bus being on the Unibus (Fastbus for the
memory, Massbus for the disk drive).
There's a block diagram of the Fastbus controller giving a high-level
overview of how this is wired in DEC drawing D-BD-MS11-0-1, in the
MS11-B MOS Memory Engineering Drawings. There's a PDF on Bitsavers (in
dec/pdp11/memory, IIRC).
From: Eric
Smith
The 11/45 (or 11/50, 11/55) Fastbus memory, whether MOS or bipolar, is
not directly on either Unibus
Actually, my understanding is that it is on UNIBUS B (or 2), via a second port
to the memory; And of course if you connect the
two UNIBI together, it's therefore directly on UNIBUS A (or 1), as well. I.e.
DMA devices can do transfers to/from it.
To a first approximation, the two Unibuses are *always* jumpered
together. If you split them and put a DMA device on Unibus B, there is
no way to tell the DMA device to initiate an operation. The RH11
Massbus adapter is a potential exception to that, because like the
11/45 CPU it has two Unibuses, so if you had no other DMA devices, you
could keep the two Unibuses split. I don't think DEC sold or supported
such a configuration.