21 Mar
2004
21 Mar
'04
1:01 p.m.
Paul Koning wrote:
Place and route is the one that I find myself fighting with. Things
like: (a) run a synthesis, with pins unlocked. (b) just to check
things, run the exact same design with the pins locked to what (a)
chose. Result: synthesis fails, not enough room. #&@$*(#@* so how
is a person supposed to create a design that can be tweaked and still
work on the same PCB layout?
Heh. I thought it was just me that had that problem :-) (trying to
squeeze 5.1lbs in to a 4.995lbs bag :-)
I was just concidering this same point this morning. I think the trick
is to try out several variations before you layout the pcb and keep the
utiltization under 70%...
I often have to fiddle endlessly to get some designs to fit (and use the
correct pins).
(I generally pick xilinx parts which have a 2x size with the same pinout
just in case)
Answer: this is normal. Gronk. I guess it's a
trick to make you buy
bigger FPGAs...
ahah! :-)
-brad