27 Apr
2008
27 Apr
'08
10:42 a.m.
Date: Sat, 26 Apr 2008 20:58:36 +0100 (BST)
From: Tony Duell
Not really. The paging registers are indeed a '670, ut only 3 locations
are used. The Read Address lines (RA and RB) are tied to the DACK2/ and
DACK3/ outputs of the 8237 DMA chip, which means that location 00 is
never used (the 8237 can never assert DACK2 and DACK3 at the same time)
and that channels 0 and 1 share a paging register.
It probably doesn't matter too much in the PC since channel 0 was
supposed to be used for refresh (and thus the page is irrelevant), but....
The FTS-88 had a '148 priority encoder (IIRC) between the DMA cotnroller
and the paging register (again a '670 I think), thus giving a separate
regsiter for each channel.
[...]
Another silly thing is that refresh was
controlled by a DMA channel. I'm
sure it saved a couple chips, but it meant that errant, or
And, indeed, using the 8237 DMA chip with a paging register (and not even
doing that as elegantly as the FTS-88 did, which at least had one paging
register per DMA channel) rather than using the 8089 'I/O processor'.
The 5150 has 4 page registers, one for each DMA channel (an LS670 4x4
RAM). Of course that limits one to doing DMA inside of 64K physical The 8089 was pretty much of a dead-end product;
limited to 20 bits of
addressability, expensive, with only 2 DMA channels. I never did
IMHO the only reason it was limited to 20 bits of address was that it was
designed to be used with the 8086/8088 (also 20 bit address). Had the
8089 become widly used (read : had IBM used it in the PC), you can bet
there'd have een am 80289, 80389, etc.
-tony