28 Jun
2001
28 Jun
'01
7:56 a.m.
On Thu, 28 Jun 2001, Jeff Hellige wrote:
Well, based on this freely available PDF version of the MindShare EISA
System Architecture book. EISA has these improvements over ISA:
* Supports intelligent bus master expansion cards.
* Improved bus aribitration and transfer rates.
* Facilitates 8, 16, or 32-bit data transfers by the main CPU, DMA,
and bus master devices.
* An efficient synchronous data transfer mechanism, permitting single
transfers as well as high speed burst transfers.
* Allows 32-bit memory addressing for the main CPU, DMA devices, and bus
master cards.
* Shareable and/or ISA-compatible handling of interrupt requests.
* Automatic steering of data during bus cycles between EISA and ISA
masters and slaves.
* 33MB/s data transfer rate for bus masters and DMA devices.
* Automatic configuration of the system board and EISA expansion cards.
The book can be found at:
http://www.mindshare.com/pdf/eisabook.pdf
-brian.
on 6/28/01 1:12 PM, Brian Chase at bdc(a)world.std.com
wrote:
There's
EISA. I thought it was an okay bus while maintaining backwards
compatibility with ISA. It'd have been more successful if it were
cheaper. As for other non-jumpered busses, Sun's Sbus is nice.
Didn't EISA also suffer from still being slow? I seem to remember that
it didn't gain much/any speed over ISA, just that the data path went from 16
to 32bits, allowing it to move more data at the same bus speed? To remain
compatible with ISA, it would seem they'd have to retain the original bus
speed as well.