4 Aug
2011
4 Aug
'11
11:37 a.m.
I am also reading the "pdp11 bus handbook"
to educate myself about the
Unibus protocoll. Intention is to hook up a scope or logic analyzer to
the bus and try to capture bus transactions. Unfortunately the book
doesn't talk abut SPC slots and the HALT signals are a SPC only.
Eh? The SPC signasl are a rearrangement of the Unibus signals (those
found on the A/B conenctor at the end of the CPU backpalen, for example).
That's why a simple backplane with no logic can provide SPC slots from a
Unibus cable.
The HALT signal is not, AFAIK, a Unibus signal at all. It's a 'local'
signal between the PCU and the console controller. These boards (CPU and
console) have to be plugged int toe hright slots of the special CPU
backplane as a result.
Incidentalluy lookign at Unius cycles with a logic analyser is quite
easy. I normally trigger on the falling edge of MSYN, qalified by the
address lines. You need a lot og LA channels to be useful, though.
-tony