Core memory emulator using non volatile ram.

Before boot ROMs, it was standard practice to toggle the boot loader into core where it would be available indefinitely, including across power cycles. You can see this in the PDP-8, and it was also documented in the early days of the PDP-11 (though in 1973 I didn't have to do this, we had a 16-word diode matrix boot ROM). RSTS-11 V4 had optional power fail handling, which would allow it to continue running after a power cycle. Not by rebooting as later versions did, but by continuing from where it left off. It would have to reinitialize the I/O devices since I/O registers are volatile, but the OS in memory would be intact and logged in user sessions would be preserved. I actually saw that work once, pretty neat. For all this, the only necessary memory property is simply that the contents was preserved across power cycles. None of the other details of core memory are important. For that matter, core memory details such as destructive read weren't visible to the CPU; the read/restore cycle was handled inside the core memory logic. That's typical; one exception I know of is the CDC 6000 series peripheral processor, which I mentioned before: there the restore cycle is part of the main execution pipeline. That's why readstart (system reboot) drops a zero in memory, it disrupts that read/restore cycle. paul