29 Apr
2013
29 Apr
'13
8:59 a.m.
On Apr 29, 2013, at 10:36 AM, ben <bfranchuk at jetnet.ab.ca> wrote:
On 4/28/2013 2:34 PM, Andy Holt wrote:
Yes, the static timing analyzers are really built for synchronous
designs. You can do asynchronous logic with glitches, but you
then have to carry a strobe with you, which almost defeats the
point. There's an FPGA company called Achronix whose first FPGA
offerings claimed to be reaping the benefits of clockless logic,
but I don't see that anywhere in their literature now (their name
still belies their origins, though).
Clockless logic is something that comes up now and then in ASIC
and FPGA circles, but it never seems to pan out (I remember Sun
doing something with it about a decade ago as well). I don't
know if it's because the tools are too hard to design or what,
but there must be some reason it never comes to anything (or at
least hasn't since the late '60s).
- Dave
While on the subject of Atlas and referencing
another thread on this list it
would be a /real/ challenge to implement on an FPGA -
Not for the lack of circuit diagrams (I understand several copies still
exist)
Not for the use of "wired-or" (don't know if Atlas used this logic
technique, but several later Ferranti machines did)
But because it used asynchronous logic which is contrary to the design
philosophy of FPGAs (and almost all other modern logic for that matter)
It justs fucks up the timing routines. I have allways thought the async
logic requires glitch free gates, and that may be a problem.