CPU design at the gate level

This isn't as unrealistic as it might seem at first glance. That's the core of what FPGA's are. Each "CLB" configurable-logic-block, or whatever the marketing term is this week, has a set of inputs, address lines, if you will, a lookup table RAM, and an output bit. This is accompanied with an output register (implemented in the LUT ramblock, based on the this-state-next-state equations for the flipflop type), and a multiplexer to bypass that register in cases where it's not wanted. The RAM that contains the lookup table also contains the steering term to that multiplexer, in the form of a feedback bit from the lookup table, and, of course, an XOR buffer by means of which the output can be set to positive or negative logic (logically implemented in the RAM as well). All this can be readily mapped into a memory. Figuring out the optimal way to do that is, of course, what keeps the FPGA makers in business. There are all kinds of strategies trading off virtual logic performance versus virtual routing capability (which is really also controlled by more RAM locations as well as by how the functions are mapped in to the RAM. It's all virtual, though. It requires a big RAM, though, in both width and depth. FPGA's today, are made with some of those resources physical rather than virtual, including, say, the mux's, registers, and buffers. However, back in the '80's, some "hardware simulators" consisted of little more than a huge RAM array with very complex software for optimizing the allocation of feedback and replication. (replication requires more RAM bits, but simplifies and speeds up certain logical constructs by eleiminating the need for multiple feedback paths for a single function. I'm sure it's not hard to envision building any logical construct in a very deep, very wide memory. Dick ----- Original Message ----- From: "Hans B Pufal" <hansp(a)aconit.org> To: <classiccmp(a)classiccmp.org> Sent: Monday, November 05, 2001 12:50 PM Subject: Re: CPU design at the gate level