25 Jul
2011
25 Jul
'11
1:20 p.m.
So I started checking caps but I've realised I'm out of my depth when it
comes to analogue electronics. I'll come back to it though.
I hope so...
What I'm not seeing is any terminal output. I
discovered there's a small
2A fuse on the quad serial card (DLV11-J) which had blown. Replaced this
and now have the correct -12V on that card. Still no activity on Tx
though. I've double checked all the jumpers on that card, port 3 is set
for the console address, 9600 baud, RS232. I've checked the Tx pin on
the UART and no activity there also, so it's not a line driver issue.
Is anything evr being written to the UART? There is a tranmit register
load input (IIRC) that should pulse when the CPU write to the UART chip.
Does it?
Bear in mind I'm new to the PDP-11 so all this is taking some time since
Now My mINC has a PDP11/45 CPU. No, that's not a typo. I have a MINC
chassis (for the IBV11 and MINC modules) hung off a DW11B on a PDP11/45
Unibus. This means I know less about the 11/03 CPU than perhaps I should od.,
I'm learning as I go ;) Digging a little further I
found the ODT is
actually implemented as microcode on the CPU (M7270/KD11). There's a
pair of jumpers on the CPU card that determine the boot method and I've
changed these to boot straight to ODT. I'm trying to build the simplest
possible system at the moment to get anything working. If I've
understood corectly then just having the CPU+serial card should get me
the '@' ODT prompt. It doesn't. I've tried other combinations of
CPU+memory+serial+BDV etc.
I think ou need some RAM memory for it to work properly. I don;t think
the grant chains are an issue at this point, but I'd put the CPU in the
far right slot (where it was origianly), then memory immediately to the
left of itm then the serial board -- with no gaps between them. The MINC
backplane is one with CD interconnect, and all the dual-height boards go
in the rear pair of connectors.
Other things I've checked : The CPU has all 4 clocks and correct
voltages. The UARTs have clock and correct voltages. The bus lines are
being pulled high (by the CPU card I think).
Probing further the bus signals BSYNCL, BDOUTL etc. all seem to be
pulsing so _something_ is happening. What I have noticed and doesn't
seem right is during a BDOUTL cycle some of the data/address (BDALxL)
lines are oscillating at high frequency, i.e. for the whole period that
BDOUTL is low the BDALxL lines oscillate (around 20-30 times per BDOUTL
period). Does anyone have any ideas what could be wrong here?
That can't be right. They should be stable throughout the cycle.
When you say 'some', is there anything in common between them (are they
all driven by thge same IC which might be malfucntioing)? And what is the
frequency (and does it relate to other frequencies in the machine, like
ther master clock)?
-tony