2 Jul
2008
2 Jul
'08
6:13 p.m.
Ethan,
According to the Motorola datasheet - " All voltages referenced to Vss ( 0V)
and Vbb ( -5 Volts ) must be applied before and removed after other supply
voltages ".
What exacerbates things is that the current spikes from all the chips are
perfectly lined up during the RAS* cycle, but the biggest hit is on the Vdd
line ( +12 Volts ). If they don't already have a 0.1 uFd across each chip on
the Vdd I'd add one. I agree the 7660 should be okay on the - 5 Volts.
Also, don't think these will run at -63 C ( ha ha ha ).
Stay warm, Best regards, Steven
On Wed, Jul 02, 2008 at 01:41:21PM -0400, Dave McGuire
wrote:
Yes... ;) indeed.
-ethan
--
Ethan Dicks, A-333-S Current South Pole Weather at 2-Jul-2008 at
17:40 Z
DRAM chips tend to draw spikes of current
during refresh, as those
little capacitors get charged.
Sure... I'm used to that with +5V-only chips like the 4164 and
up, but I don't have any design experience with the multi-voltage
parts, thus my caution.
If you have adequate low-impedance
bypassing to supply those short-term demands, things should be fine
with the 7660. It's a fairly predictable and dependable chip.
By low-impedance bypassing, you mean monolithic (not electrolytic) caps,
or do you mean something else?
... I
wouldn't be able to get an order from Digikey for nearly 4
months in any case. I have to use what's on hand.
Good heavens, one would think you're in Antarctica or something.
Oh, wait.. ;) South Pole Station
PSC 468 Box 400 Temp -81.9 F (-63.3 C) Windchill -121.1 F (-85.1
C)
APO AP 96598 Wind 10.8 kts Grid 46
Barometer 680.7 mb (10602
ft)
Ethan.Dicks at usap.gov
http://penguincentral.com/penguincentral.html