MC68010 (was Re: Stupid lusers...)

On Fri, 5 Jun 1998, Zane H. Healy wrote: I had a 68010 in my A1000 for a few years, until I bought my A1200 and put the 68000 back. The amount of speed increase the 68010 brought very much depended on the software being used. Turbo Silver (which IS classic ray tracing software) only sped up by about 5%-7%, depending on the scene being rendered. That's less than it was hyped-up to do, and unfortunately that's the only software I timed before and after the 68010 installation. And indeed, some software wouldn't work anymore. That was generally not a problem for software that didn't kill the OS, because you could run something called 'decigel' which would trap the illegal instruction (MOVE SR, which became available only in supervisor mode). The calculator program distributed with Workbench 1.1 used this instruction, as did Transformer. Transformer had to be patched to run on anything but the 68000. Some commercial games and some demos I've got also won't work with the 68010, which is why I replaced the 68000 when I no longer had need of the "speed". The following is part of the "mc68010.ins" file I downloaded from a BBS many years ago, which convinced me to try the 68010 (and no, I didn't understand everything in the file, but I found an '010 for $Can30 and said 'what the heck'): -------------------------------------------------------------------------- III. M68000 MICRO MINUTES (c) Motorola MM-444-02 Advantages of Upgrading an MC68000 to an MC68010 There are several ways a system's performance can be upgraded. Some are software related, such as lowering operating system overhead, obtaining better quality language compilers, wisely designing application programs, and coding applications more efficiently. Others are hardware related, such as adding memory, improving I/O channel data rates, increasing mass storage speed and capacity, reducing memory access times, and upgrading the system processor's clock frequency. When considering an MC68000 system upgrade to higher performance, the obvious thought is to redesign for a higher frequency MC68000. For example, a current MC68000 system running at 10 MHz could be redesigned to run at 12.5 MHz, thereby increasing system throughput by 25%. The "obvious solu- tion", however, is not necessarily the most appropriate or cost-effective once several factors are taken into consideration and alternative solutions examined. The speed-up of a system clock will not be effective unless the system's memory access time is also improved. The performance of the MC68000 is strictly limited by the bus speed, and if no improvement in memory speeds are available, then an increase in system clock speed will lead to negligible improvement in the overall result. A 10 MHz processor running with no "wait states" utilizes a 400 nS bus cycle (4 clocks x 100 nS/clock). This same bus cycle timing, however, leads to a wait cycle on a 12.5 MHz processor (4 clocks x 80 nS/clock + 80 nS of idle time). Thus, the bus performance is exactly the same, but the faster processor is idled for one complete clock cycle. Since a decrease in the bus cycle time provides a directly proportional increase in processor throughput (until, of course, the memory cycle becomes faster than the fastest processor bus cycle), the 12.5 MHz processor has no relative performance advantage over the 10 MHz system. The bottom line, then, is that in order to be effective, a higher speed processor must run with fewer or the same number of "wait states". This normally requires a redesign of the memory subsystem to improve the memory access time. Referring to the MC68000 Data Manual (ADI-814-R4), the memory access re- quirements for the various speed processors can be examined. The effective memory access time (Taccs) of the MC68000 to a memory array (from assertion of Address Strobe [-AS] to data valid) is: Taccs = Tch + 2Tcyc - Tchs1 - Tdic1 + (n * Tcyc) where: Tch is the clock high time (system dependent) Tcyc is the clock period of the processor clock Tchs1 is the delay time from the rising edge of the clock to the assertion of address strobe Tdic1 is the data input set-up time prior to the falling edge of the clock n is the number of wait cycles in the system Assuming a symmetric clock (50% duty cycle), the memory speed required for a no "wait-state" bus cycle for a 19 Mhz MC68000 processor is 185 nS (50 + 200 - 55 -10 + 0). This bus speed can be easily realized with readily available 150 nS dynamic RAMs and careful system design. However, with the same assumptions, the memory speed required for a no "wait-state" bus cycle on a 12.5 Mhz processor is reduced to 135 nS (40 + 160 - 55 - 10 + 0) which presents an obvious problem to the cost-conscious system designer -- lack of cost-effective, large capacity 100 nS RAMs! Memory access times are not the only difficulty encountered with the faster clock speeds. In a similar vein, the design of an efficient 12.5 MHz system is more difficult than that of a 10 MHz system, since more careful attention must be paid to the physical design of the board in order to account for the higher frequency signals present, and the increased sensitivity to transient phenomena. A "painless" alternative means to EFFECTIVELY increase system performance is to upgrade to the MC68010 processor. The MC68010 at equal clock fre- quencies will run from 8% to 50% faster than an MC68000 without any user code changes. The speed-ups are due to several microcode enhancements: many 32-bit operations, conditional branches, multiply, divide and other miscellaneous instructions run faster. Systems which use memory management can have dramatic improvements with slight operating system changes utilizing a few new MC68010 instructions such as "Move to/from Address Space" (MOVES). Systems may see a significant improvement if they heavily utilize multiply, divide and looping operations. Loops run from 23% to 80% faster once the microcode sets up the automatic "loop mode". Such loops benefit particular functions such as block moves, character matching and general string manipulation operations, and multiple-precision binary and packed BCD arithmetic. The new MC68010 multiply is 14 clocks faster, and the divide is 32 clocks faster than the MC68000. Programs utilizing (or with the potential of utilizing) such operations can obtain an increase in perfor- mance easily exceeding 10%. An additional "plus" of the MC68010 is the provision of a clear path for the upgrade of current operating systems to full virtual operating systems utilizing the sophisticated virtual memory processing capabilities of the MC68010 (which is the same virtual environment offered by the 32-bit MC68020). Since the MC68010 is pin-for-pin compatible with the MC68000, *NO* hardware redesign is necessary. Only very minor software changes may have to be made depending on operating system conventions. The MC68010 differs from the MC68000 in that: 1) a generic "vector word" has been added to the MC68010 stack frame; and 2) the MC68000's "MOVE SR,ea" has been made a privileged operation. Easy software solutions for these two minor differences are: 1) any routines which build exception stacks (e.g. those which dispatch a routine via an RTE instruction) are modified to account for the four word stack frame (the MC68000 uses a three word stack frame); and 2) an exception handler is added to provide for privilege violations generated by the execution of the "MOVE SR,ea" instructions in the USER state (local Motorola representatives can supply a debugged handler to suit the requirements of any OS). Major operating systems have been ported from the MC68000 to the MC68010 in less than a single day, reflecting the trivial changes required in the super- visory level code. The bottom line is, by upgrading an MC68000 system to an MC68010 system, an increase in system performance is obtained which is equal to that which a system redesign from 10 MHz to 12.5 MHz would provide, but with signifi- cantly less design cost and effort. The "speed-only" upgrade could only achieve, at best, a 25% system improvement, and only if the system memory access time is significantly improved. The MC68010 upgrade offers from 8% to 50% improvement. Note that the speed gained by changing to the MC68010 is achieved with NO change in memory speeds, NO board redesign, and NO higher speed parts installed in the system as would be required to upgrade a system to a 12.5 MHz part. ---------------------------------------------------------------------------- Doug Spence ds_spenc(a)alcor.concordia.ca http://alcor.concordia.ca/~ds_spenc/