17 Nov
2010
17 Nov
'10
3:27 p.m.
They had non-multiplexed addresses I think. Later
DRAMs had multiplexed
address inputs. of course. Was there a good reason for this other than to
save package pins?
I wouldn't call it a necessity but the RAS/CAS/refresh coordination
works out very nicely when address inputs are multiplexed in this way.
So much so that I can't think of a DRAM since the 4116 that hasn't used this
scheme.
SRAM's almost always have the concepts of "row" and "column"
select
internally but rarely is it obvious from the outside.
Tim.