4 Jan
2006
4 Jan
'06
4:46 p.m.
Roy J. Tellason wrote:
Zero operands Hmm 0 + 0 -> 0 , 0 - 0 -> 0, branch if 0 ...
But the catch is the stack(s) for most 0 operand machines is local
memory and often
256 words or so. In a FPGA that is only few ns of access time.
Ben alias Woodelf
You're probably right, but I don't think
I'd want to go there anyhow.
Considering the seriously low speed of some of those early 8-bit parts it
wouldn't be at all hard to improve on it. Heck, I know of a lot of people
that went to some nontrivial effort to do things like upgrade a stock Kaypro,
and I remember thinking how nifty it'd be when I first heard about a 20 MHz
z80 coming out. And with simple programs and efficient design you could get
some good results out of such a setup.
Still dreams of having a 2 MHZ Gimix 6809 .... Level II OS/9 and a nice HD.
The only CP/M machine I ever used had flakey 8 inch drives thus I don't
quite have
fond memories of that!
Still, there
are a number of processor models that make sense
for using slower memory. I've seen one that used a 20 bit data
bus and most instructions were 5 bits. This means that 5 operations
can be done on one instruction fetch. This doesn't work well
with the typical RISC machine because you need operands.
It does work with zero operand machines quite nicely :)
Yep, I imagine it would. :-)