26 Jan
2011
26 Jan
'11
4:38 p.m.
On 1/26/2011 6:27 PM, Philip Pemberton wrote:
On 26/01/11 20:29, Keith M wrote:
Close! A DE0. It has a much more capable, but smaller Cyclone III. (15k
vs 18k LEs on DE1) I like the m9k's in Cyclone III instead of m4k's.
My chip is actually a
A3V64S40ETP is organized as 4-bank x 1,048,576-word x 16-bit Synchronous
DRAM with LVTTL interface.
http://www.zentel.com.tw/download/A3V64S40ETP_v1.1_Zentel.zip
(sorry for zipped pdf)
You're using an Altera/Terasic DE1 (Cyclone II Starter Kit) developer
board, aren't you? Sometimes it's less effort to write code from
scratch than to try and
make someone else's code work...
Sure. I like doing this when I've got a chance of actually succeeding. :)
If I had unlimited free time then it would be on my list.
Wasn't there something about time and skill being interchangeable? If
you lack in one, the other makes up for it. Or something like that?
Oh, the Milkymist SDRAM controller core... That should
work quite
nicely. Sebastien Bordeauducq is a frickin' good HDL coder...
I've been picking his brain recently. Although he's a super-coder, and
I'm still, well, closer to the beginning than the end. :) So he has a
tendency to underestimate the time/skills/knowledge necessary to do
something. I've been chatting with him this week.
You could have an SRAM-like interface, you'd just
need to have a BUSY or
DTACK output to go with it. Is that close enough?
Either way, you're not getting rid of the BUSY output...
Yup. That's basically what I imagined. Once the data is "ready",
something is asserted or cleared, and then you read the data.
Definitely what I had in mind.
Thanks
Keith