Clocking (was Re: RFC Ethernet Bus Interface V1)

On 1/5/14 8:08 PM, Philipp Hachtmann wrote: I've been designing digital logic since the 70's. Wrapping my head around someone else's large project, be it in a HDL or some hairball of C++ out of a SVN repository is the problem :-) Understanding digital stuff IS simple, if you have a single clock domain. Looking at how large blocks of logic are clocked is one of the first thing that I look at. Understanding how the DECtape interfaces work again has been fun. Think about building a peripheral interface where your input clock varies +/- 10% All sorts of fun things to look at in old CPUs as far as how they were clocked. I was scanning in the Burroughs B 5500 drawings recently and didn't know the system was designed with a single distributed 1MHz clock. The early DEC CPUs, in the MIT tradition, have a pulse that ripples down through the logic, popping out at the other end to start the cycle over again. I've been told, but haven't verified that the Interdata 8/32 works the same way. I think the farthest I dug into that was to notice that the CPU has no clock oscillator.