TTL HEX LED driver chip

Personally I'd rather have the original processor in 80 (or so) simple logic chips and ROMs, but anyway... There are many sources of information on these machines, there's probably enough infroamtion out there to recreate them. THe patents for these machines (separate ones for the 9810, 9820 and 9830) are very informative and include schematics and firmware listings for the prototypes and some their options. Th production machines do differ in some details, so be caareful if you use this information to repair one. I can't rememebr the patent numbers, but I think they're on Eric Smith's site (http://www.brouhaha.com/), or I can see if I can dig them out. There's a lot of information (user manuals, HP service manuals (boardswapper guides) and schematics) on http://www.hpmuseum.net/ There's an hp9800 emulator (I can't rememebnr what it runs on...) which includes dumps of the firmware ROMs. I think it's linked from sourceforge. I have dumps of the CPU micorocde and ALU roms. I also have an annotated CPU microcode source listing. I'll be happy to make thes available. For reference, here's the CPU microcode word format : HP98x0 microcode word bits --------------------------- 0 : Toggle uA4 ) 1 : Toggle uA5 ) Select condition (Qualifier) 2 : Toggle uA6 ) 3 : Toggle uA7 ) 4 : Toggle uA1 5 : Toggle uA2 6 : Toggle uA3 7 : Toggle uA0 8 : ) 9 : ) Number of shift clocks - 1 10 : ) 11 : ) 12 : Rd A/B (If R=0, QmuJMP, if R=1, I/O operation) 13 : ALU(1) 14 : ALU(0) 15 : IQN (Inhibit shift clock by condition) 16 : R(2) 17 : R(1) 18 : R(0) 19 : Enable condition 20 : ALU(2) 21 : X(1) 22 : X(2) 23 : X(0) 24 : ALU S input control SC(1) 25 : ALU S input control SC(0) 26 : ALU -> T register 27 : ALU -> M register SC(1) SC(0) 0 0 0 -> S_ALU 0 1 M -> S_ALU 1 0 T -> S_ALU 1 1 1 -> S_ALU R(2) R(1) R(0) 0 0 0 1 -> R_ALU 0 0 1 P -> R_ALU 0 1 0 T -> E, E -> R_ALU 0 1 1 Memory Write (Treg -> memory) 1 0 0 ALU -> Q(6) 1 0 1 Q -> R_ALU 1 1 0 Memroy Read (memory -> Treg) 1 1 1 0 -> R_ALU X(2) X(1) X(0) 0 0 0 ALU -> Q 0 0 1 Q(11) -> A/B select Flip-Flop, clear BCD carry 0 1 0 ALU BCD mode 0 1 1 ALU -> E, E -> R_ALU 1 0 0 Invert A/B select Flip-Flop 1 0 1 ALU -> P 1 1 0 ALU -> A/B 1 1 1 None of the above If X=3 and R=2, then ALU -> A/B (not E), E->R_ALU, and 0->E ALU(2) ALU(1) ALU(0) 0 0 0 XOR 0 0 1 AND 0 1 0 IOR 0 1 1 Zero 1 0 0 Zero, clear carry 1 0 1 IOR, clear carry 1 1 0 IOR, set carry 1 1 1 Add Conditions 0 : Q(0) 1 : Q(1) 2 : Q(2) 3 : Q(3) 4 : Q(4) 5 : Q(5) 6 : Q(6) 7 : Carry 8 : P bit 0 9 : Q(15) 10 : Memory reference instruction 11 : Q(10) 12 : I/O flag 13 : Q(8) 14 : BCD Carry 15 : I/O running And the CPU machine code instruction set : Memory Reference 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADA IND 0 0 0 0 Z/C | Address | ADB IND 0 0 0 1 Z/C | Address | CPA IND 0 0 1 0 Z/C | Address | CPB IND 0 0 1 1 Z/C | Address | LDA IND 0 1 0 0 Z/C | Address | LDB IND 0 1 0 1 Z/C | Address | STA IND 0 1 1 0 Z/C | Address | STB IND 0 1 1 1 Z/C | Address | IOR IND 1 0 0 0 Z/C | Address | ISZ IND 1 0 0 1 Z/C | Address | AND IND 1 0 1 0 Z/C | Address | DSZ IND 1 0 1 1 Z/C | Address | JSM IND 1 1 0 0 Z/C | Address | JMP IND 1 1 0 1 Z/C | Address | Shift 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AAR 0 1 1 1 0 X X | Shift | X 0 0 0 0 ABR 0 1 1 1 1 X X | Shift | X 0 0 0 0 SAR 0 1 1 1 0 X X | Shift | X 0 0 1 0 SBR 0 1 1 1 1 X X | Shift | X 0 0 1 0 SAL 0 1 1 1 0 X X | Shift | X 0 1 0 0 SBL 0 1 1 1 1 X X | Shift | X 0 1 0 0 RAR 0 1 1 1 0 X X | Shift | X 0 1 1 0 RBR 0 1 1 1 1 X X | Shift | X 0 1 1 0 Skip/Alter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SZA 0 1 1 1 0 0 | Skip Offset | 0 1 0 0 0 SZB 0 1 1 1 1 0 | Skip Offset | 0 1 0 0 0 RZA 0 1 1 1 0 1 | Skip Offset | 0 1 0 0 0 RZB 0 1 1 1 1 1 | Skip Offset | 0 1 0 0 0 SIA 0 1 1 1 0 0 | Skip Offset | 1 1 0 0 0 SIB 0 1 1 1 1 0 | Skip Offset | 1 1 0 0 0 RIA 0 1 1 1 0 1 | Skip Offset | 1 1 0 0 0 RIB 0 1 1 1 1 1 | Skip Offset | 1 1 0 0 0 SLA 0 1 1 1 0 S | Skip Offset | C 1 0 0 1 SLB 0 1 1 1 1 S | Skip Offset | C 1 0 0 1 SAM 0 1 1 1 0 S | Skip Offset | C 1 0 1 0 SBM 0 1 1 1 1 S | Skip Offset | C 1 0 1 0 SAP 0 1 1 1 0 S | Skip Offset | C 1 0 1 1 SBP 0 1 1 1 1 S | Skip Offset | C 1 0 1 1 SES 0 1 1 1 0 S | Skip Offset | C 1 1 0 0 SEC 0 1 1 1 1 S | Skip Offset | C 1 1 0 1 Register Reference 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADA 0 1 1 1 A/B X X IND 0 0 0 0 1 1 1 1 ADB 0 1 1 1 A/B X X IND 0 0 0 1 1 1 1 1 CPA 0 1 1 1 A/B X X IND 0 0 1 0 1 1 1 1 CPB 0 1 1 1 A/B X X IND 0 0 1 1 1 1 1 1 LDA 0 1 1 1 A/B X X IND 0 1 0 0 1 1 1 1 LDB 0 1 1 1 A/B X X IND 0 1 0 1 1 1 1 1 STA 0 1 1 1 A/B X X 1 0 1 1 0 1 1 1 1 STB 0 1 1 1 A/B X X 1 0 1 1 1 1 1 1 1 IOR 0 1 1 1 A/B X X IND 1 0 0 0 1 1 1 1 ISZ 0 1 1 1 A/B X X 1 1 0 0 1 1 1 1 1 AND 0 1 1 1 A/B X X IND 1 0 1 0 1 1 1 1 DSZ 0 1 1 1 A/B X X 1 1 0 1 1 1 1 1 1 JSM 0 1 1 1 A/B X X 1 1 1 0 0 1 1 1 1 JMP 0 1 1 1 A/B X X IND 1 1 0 1 1 1 1 1 DMA/extras 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMA 0 1 1 1 0 X X X X X 1 0 1 1 1 0 CMB 0 1 1 1 1 X X X X X 1 0 1 1 1 0 TCA 0 1 1 1 0 X X X X X 1 1 1 1 1 0 TCB 0 1 1 1 1 X X X X X 1 1 1 1 1 0 EXA 0 1 1 1 0 X X X X X 0 0 1 1 1 0 EXB 0 1 1 1 1 X X X X X 0 0 1 1 1 0 CMA 0 1 1 1 0 X X X X X 0 1 1 1 1 0 I/O group 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STF 1 1 1 1 X 1 0 1 1 1 1 | Select Code | CLF 1 1 1 1 X 1 1 1 1 1 1 | Select Code | SFC 1 1 1 1 X 1 H/C 1 1 1 0 | Select Code | SFS 1 1 1 1 X 1 H/C 1 0 1 0 | Select Code | CLC 1 1 1 1 X 1 H/C 1 0 1 1 | Select Code | STC 1 1 1 1 X 1 H/C 1 1 0 0 | Select Code | OT* 1 1 1 1 A/B 1 H/C 0 0 1 1 | Select Code | LI* 1 1 1 1 A/B 1 H/C 0 1 0 1 | Select Code | MI* 1 1 1 1 A/B 1 H/C 0 0 0 1 | Select Code | Macro Group 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 MOV 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 CLR 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 XFR 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 MRX 1 1 1 1 1 0 0 1 0 0 0 1 1 0 0 0 MRY 1 1 1 1 1 0 0 1 0 0 1 1 1 0 0 0 MLS 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 DRS 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 DLS 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 FXA 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 0 FMP 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 FDV 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 CMX 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 CMY 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 MDI 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 NRM 1 1 1 1 0 0 1 1 0 0 1 0 1 0 0 0 I am happy to chat about these fine amchines (I have a 9810, 9820 and 9830, all fo which I've reparied...) as much as you like :-) -tony